Munich, Germany – Transaction-level modeling got a hard look at the recent Design Automation and Test in Europe (DATE) conference here as a possible answer to some of the design and verification ...

IP companies have heralded a new age in platform-based design for years – ever since semiconductor integration capacity reached the point where entire systems could theoretically be integrated into a ...

System-on-Chip (SoC) designs are becoming increasingly complex. Modelling, verification, and debug facilities at RTL have become quite inadequate in the face of rising design challenges.

Transaction-level modeling (TLM) verification methodologies are propagating down from power users, such as large systems houses and integrated device manufacturers, to the broader design community. As ...

With design complexity always on the rise and an increasing amount of embedded software encapsulation in designs today, engineering teams need to be concerned with power consumption in the initial ...

Virtualized Systems Development Platform Provides Full Support for Multiple Modeling Languages SAN JOSE, Calif. -- Jul 27, 2009 -- Virtutech®, Inc., the leader in virtualized systems development (VSD) ...

SLD: How long has NXP designed at the system-level for production chips? Frans Theeuwen: It depends on what you call ‘system-level design.’ We have been doing hardware/software co-verification ...